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| TS2026L Dual-Channel Power Distribution Switch Pin assignment: 1. ENA 2. FLGA 3. FLGB 4. ENB 5. OUTB 6. GND 7. IN 8. OUTA 140m max. on-resistance per channel 2.7V to 5.5V operating range Under voltage lockout General Description The TS2026L is high-side MOSFET switches optimized for general-purpose power distribution requiring circuit protection. The TS2026L are internally current limited and have thermal shutdown that protects the device and load. When a thermal shutdown fault occurs, the output is latched off until the faulty load is removed. Removing that load or toggling the enable input will reset the device output. Both device employ soft-start circuitry that minimized inrush current in application where highly capacitive loads are employed. A fault status output flag is asserted during over current and thermal shutdown conditions. Transient faults are internally filtered. Features 140m max. on-resistance per channel 2.7V to 5.5V operating range 500mA min. continuous current per channel Short-circuit protection with thermal shutdown Thermal isolated channels. Fault status flag with 3ms filter eliminates false assertions. Under voltage lockout Reverse current flow blocking (no "body diode") Logic-compatible inputs Soft-start circuit Low quiescent current Applications USB peripherals General purpose power switching ACPI power distribution Notebook PCs PDAsPC Card hot swap Ordering Information Part No. TS2026LCS Operating Temp. (Ambient) -40 ~ +85 C o Package SOP-8 Absolute Maximum Rating Supply Voltage Fault Flag Voltage Fault Flag Current Output Voltage Output Current Enable input Storage Temperature VIN VFLG IFLG VOUT IOUT IEN TSTG +6 +6 25 +6 Internal Limited -0.3 ~ +3 -65 ~ +150 V o V V mA o C C TS2026L 1-7 2005/11 rev. A Typical Application Block Diagram TS2026L 2-7 2005/11 rev. A Electrical Characteristics Vin=5V, TA = 25 C, unless noted o Parameter Symbol OUT = open Condition VENA=VENB2.4V (switch off), Min. -- Typ. 0.75 Max. 5 Units uA Supply Current IDD VENA=VENB0.8V (switch on), OUT = open --0.8 -- 100 1.7 1.455 250 0.01 1 90 100 -1.3 1.15 35 32 0.9 1.0 20 3 3 160 2.4 --1 -140 160 10 5 4.9 100 100 1.25 1.25 -7 -2.7 2.5 25 40 10 ----- uA V V mV uA pF m m uA mS mS uS uS A A uS mS mS V V uA o o o o Enable Input threshold Enable Input Hysteresis Enable Input Current Enable Input Capacitance Switch Resistance Note 4 Output Leakage Current Output Turn-on Delay Output Turn-on Rise Time Output Turn-off Delay Output Turn-off Fall Time Short-Circuit Output Current Current -Limit Threshold Short-Circuit Response Time Low-to-high transition VEN High-to-low transition IEN VENA= 0V to 5.5V -1 -- RDS(ON) VIN= 5V, IOUT= 500mA VIN= 3.3V, IOUT= 500mA VENX0.8V or VENX2.4V ----- tON tR tOFF tF ILIMIT VOUT= 0V, enable into short-circuit Ramped load applied to output VOUT= 0V to IOUT= ILIMIT (short applied to output) VIN=5V, apply VOUT=0V, Until FLG low tD VIN=3.3V, apply VOUT=0V, Until FLG low VIN rising VIN falling IL =10mA, VIN =5V IL =10mA, VIN =3.3V VFLAG =5V TJ increasing, each switch RL=10, CL=1F, see "Timing Diagrams" ---0.5 --1.5 Over current Flag Response Delay Under voltage Lockout Threshold Error Flag Output Resistance Error Flag Off Current 2.2 2.0 -------- 2.4 2.15 10 15 -140 120 160 150 C C C C Over temperature Threshold Note 5 TJ decreasing, each switch TJ increasing, both switch TJ decreasing, both switch Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handing precautions recommended. Note 4. For maintenance RDS140m assembly to make gold conductors in diameter 50m. o Note 5. If there is a fault on one channel, that channel will shut down when the die reaches approximately 140 C. If the o die reaches approximately 160 C, both channels will shut down, even if neither channel is in current limit. TS2026L 3-7 2005/11 rev. A Pin Description Pin 1 2 Name ENA FLGA Description Switch A Enable (Input): Logic-compatible enable input. active low (L) Fault Flag A (Output): Active-low, open-drain output. Indicated over current or thermal shutdown conditions. Over current conditions mush last longer than tD in order to assert FLGA Fault Flag B (Output): Active-low, open-drain output. Indicated over current or thermal shutdown conditions. Over current conditions mush last longer than tD in order to assert FLGB Switch B Enable (Input): Logic-compatible enable input. active-low (L) Switch B (Output) Ground Input: Switch and logic supply input Switch A (Output) 3 4 5 6 7 8 FLGB ENB OUTB GND IN OUTA Test Circuit Timing Diagram Output Rise and Fall Time Active-Low Switch Times TS2026L 4-7 2005/11 rev. A Function Description Input and Output IN is the power supply connection to the logic circuitry and the drain of the output MOSFET. OUT is the source of the output MOSFET. In a typical circuit, current flows from IN to OUT toward the load. If V OUT is greater than VIN, current will flow from OUT to IN, since the switch is bidirectional when enabled. The output MOSFET and driver circuitry are also designed to allow the MOSFET source to be externally forced to a higher voltage than the drain (VOUT > VIN ) when the switch is disabled. In this situation, the TS2026 prevents undesirable current flow from OUT to IN. Thermal Shutdown Thermal shutdown is employed to protect the device from damage should the die temperature exceed safe margins due mainly to short circuit faults. Each channel employs its own thermal sensor. Thermal shutdown shuts off the o output MOSFET and asserts the FLG output if the die temperature reaches 140 C and the overheated channel is in current limit. The over channel will be shut off. Upon determining a thermal shutdown condition. The TS2026 will o automatically reset its output when the die temperature cools down to 120 C . The TS2026 output and FLG signal will continue to cycle on and off until the device is disabled or the fault is removed. Figure 1. Depicts typical timing. Depending on PCB layout, package, ambient temperature, etc., it may take several hundred milliseconds from the incidence of the fault to the output MOSFET being shut off. This time will be shortest in the case of dead short on the output. Power Dissipation The device's junction temperature depends on several factors such as the load, PCB layout, ambient temperature and package type. Equations that can be used to calculate power dissipation of each channel and junction temperature are found below. 2 PD = RDS(ON) x IOUT Total power dissipation of the device will be the summation of PD for both channels. To relate this to junction temperature, the following equation can be used: TJ = PD x JA + TA Where: TJ = junction temperature TA = ambient temperature JA = is the thermal resistance of the package Current Sensing and Limiting The current-limit threshold is preset internally. The preset level prevents damage to the device and external load but still allows a minimum current of 500mA to be delivered to the load. The current-limit circuit senses a portion of the output MOSFET switch current. The current-sense resistor shown in the block diagram is virtual and has no voltage drop. The reaction to an over current condition varies with three scenarios. Switch Enable into Short-Circuit If a switch is enabled into a heavy load or short-circuit, the switch immediately enters into a constant-current mode, reducing the output voltage. The FLG signal is asserted indicating an over current condition. Switch Enable Applied to Enabled Output When a heavy load or short-circuit is applied to an enabled switch, a large transient current may flow until the current limit circuitry responds. Once this occurs the device limits current to less than the short circuit current limit specification. Current-Limit Response-Ramped Load The TS2026 current-limit profile exhibits a small fold back effect of about 200mA. Once this current-limit threshold is exceeded the device switches into a constant current mode. It is important to note that the device will supply current up to the current-limit threshold TS2026L 5-7 2005/11 rev. A Function Description Fault Flag The FLG signal is an N-channel open-drain MOSFET output. FLG is asserted (active-low) when either an over current or thermal shutdown condition occurs. In the case of and over current condition, FLG will be asserted only after the flag response delay time, tD, has elapsed. This ensured that FLG is asserted only upon valid over current conditions and that erroneous error reporting is eliminated. For example, false over current condition can occur during hot plug event when a highly capacitive load is connected and causes a high transient inrush current that exceeds the current-limit threshold for up to 1ms. The FLG response delay time tD is typically 3ms. Undervoltage Lockout Undervoltage lockout (UVLO) prevents the output MOSFET from turning on until VIN exceeds approximately 2.5V. Undervoltage detection function only when the switch is enabled. Figure 1. TS2026L Fault Timing TS2026L 6-7 2005/11 rev. A SOP-8 Mechanical Drawing SOP-8 DIMENSION DIM A B C D F G K M P R 0 MILLIMETERS MIN 4.80 3.80 1.35 0.35 0.40 0.10 o INCHES MIN 0.189 0.150 0.054 0.014 0.016 0.004 0 o MAX 5.00 4.00 1.75 0.49 1.25 0.25 7 o MAX 0.196 0.157 0.068 0.019 0.049 0.009 7 o 1.27 (typ) 0.05 (typ) 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 TS2026L 7-7 2005/11 rev. A |
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